A Novel Design for High Speed Multiplier for Digital Signal Processing Applications

In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per The proposed architecture, for two 8-bit numbers; the multiplier and multiplicand, each are grouped as 4-bit numbers so that it decomposes into 4×4 multiplication modules. It is also illustrated that the further hierarchical decomposition of 4×4 modules into 2×2 modules will not have a significant effect in improvement of the multiplier efficiency or in other words multiplier decomposition nearly reaches a saturation level in its efficiency at 4×4 decomposition. The coding is done in VHDL (Very High Speed Integrated Circuits Hardware Description Language) and the FPGA synthesis is done using Xilinx library. Index Terms — Vedic mathematics, vertically and crosswise algorithm, VHDL, Vedic multiplication.